The present invention relates to a semiconductor memory device, and more particularly, to a delay locked loop (DLL) of a semiconductor memory device.
A system is implemented with a plurality of semiconductor devices. Among them, a semiconductor memory device is used to store data. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from a data processor on unit cells corresponding to addresses inputted together with the data.
As the operating speed of the system increases, the data processor requires the semiconductor memory device to input/output data at a high speed. As semiconductor integrated circuit (IC) technologies rapidly develops, the operating speed of the data processor increases, but the data input/output speed of the semiconductor memory device does not keep up with the increased operating speed of the data processor.
Many attempts have been made to develop semiconductor memory devices that can increase data input/output speed up to the level required by the data processor. One of these semiconductor memory devices is a synchronous memory device that outputs data at each period of a system clock. Specifically, the synchronous memory device outputs or receives data to or from the data processor in synchronization with the system clock. However, because even the synchronous memory device could not keep up with the operating speed of the data processor, a double data rate (DDR) synchronous memory device was developed. The DDR synchronous memory device outputs or receives data at each transition of the system clock. That is, the DDR synchronous memory device outputs or receives data in synchronization with falling edges and rising edges of the system clock.
However, the system clock necessarily has a predetermined delay time until it arrives at a data output circuit because it passes through a clock input buffer, a transfer line, etc. Thus, if the data output circuit outputs data in synchronization with the delayed system clock, an external device will receive data that are not synchronized with rising edges (rising transitions) and falling edges (falling transitions) of the system clock.
To solve this problem, the semiconductor memory device uses a delay locked loop (DLL) circuit to lock a delay of a clock signal. The DLL circuit compensates for the delay caused by internal circuits of the semiconductor memory device until the system clock input to the semiconductor memory device is transferred to the data output circuit. The DLL circuit finds the delay time of the system clock, which is caused by the clock input buffer, the clock transfer line, etc. of the semiconductor memory device. Then, the DLL circuit delays the system clock by the found delay time and outputs the delayed system clock to the data output circuit. That is, the DLL circuit outputs the delay-locked system clock to the data output circuit. The data output circuit outputs data in synchronization with the delay-locked system clock. Therefore, it seems that the data are correctly output to the external circuit in synchronization with the system clock.
In an actual operation, the delay-locked system clock is transferred to the output buffer at a point in time earlier by one period than a point in time when the data must be outputted, and the output buffer outputs data in synchronization with the received delay locked clock. Therefore, the data is outputted faster than the delay of the system clock caused by the internal circuit of the semiconductor memory device. In this way, it seems that the data are correctly outputted in synchronization with the rising and falling edges of the system clock input to the semiconductor memory device. That is, the DLL circuit is a circuit to find how fast the data must be outputted in order to compensate for the delay of the system clock within the semiconductor memory device.
A data input device can receive data accurately synchronized with the system clock when the data is outputted in synchronization with the delay locked clock output from the DLL circuit. However, since the delay locked clock always has a constant frequency, an electromagnetic interference (EMI) characteristic may be degraded during the data transfer process. That is, the EMI characteristic may be degraded when a clock frequency used for data transfer between the semiconductor memory device and the data processor is fixed to a single frequency. To solve this problem, the system with the semiconductor memory device is designed to have a spread spectrum clock (SSC) function. The SSC function is to spread a power spectrum by modulating a clock received from the semiconductor memory device. However, when the SSC function of the system is operated incorrectly, the EMI characteristic is degraded because the power spectrum output from the semiconductor memory device has a single peak.